8

LTC1659

OPERATIO

Voltage Output

The LTC1659’s rail-to-rail buffered output can source or

sink 5mA over the entire operating temperature range

while pulling to within 300mV of the positive supply

voltage or ground. The output swings to within a few

millivolts of either supply rail when unloaded and has an

equivalent output resistance of 40

Ω when driving a load to

the rails. The output can drive 1000pF without going into

oscillation.

The output swings from 0V to the voltage at the REF pin,

Serial Interface

on the rising edge of the clock. The MSB is loaded first. The

DAC register loads the data from the shift register when

CS/LD is pulled high. The CLK is disabled internally when

CS/LD is high. Note: CLK must be low before CS/LD is

pulled low to avoid an extra internal clock pulse.

The buffered output of the 12-bit shift register is available

LTC1659s may be daisy-chained together by connecting

and CS/LD signals remain common to all chips in the daisy

chain. The serial data is clocked to all of the chips, then the

CS/LD signal is pulled high to update all of them

simultaneously.