LTC1410CSW datasheet(12/16 Pages) LINER

12 / 16 page

LTC1410

APPLICATIONS INFORMATION

High quality tantalum and ceramic bypass capacitors

should be used at the VDD, VSS and REFCOMP pins as

shown in the Typical Application on the first page of this

data sheet. Bypass capacitors must be located as close to

the pins as possible. The traces connecting the pins and

bypass capacitors must be kept short and should be made

as wide as possible.

The LTC1410 has differential inputs to minimize noise

coupling. Common mode noise on the + AIN and – AIN

leads will be rejected by the input CMRR. The – AIN input

can be used as a ground sense for the + AIN input; the

LTC1410 will hold and convert the difference voltage

between + AIN and –AIN. The leads to + AIN (Pin 1) and – AIN

(Pin 2) should be kept as short as possible. In applications

where this is not possible, the + AIN and – AIN traces should

be run side by side to equalize coupling.

A single point analog ground separate from the logic

system ground should be established with an analog

ground plane at Pin 5 (AGND) or as close as possible to the

ADC. Pin 14 and Pin 19 (ADC’s DGND) and all other analog

grounds should be connected to this single analog ground

point. No other digital grounds should be connected to this

analog ground point. Low impedance analog and digital

power supply common returns are essential to low noise

operation of the ADC and the foil width for these tracks

should be as wide as possible. In applications where the

ADC data outputs and control signals are connected to a

continuously active microprocessor bus, it is possible to

get errors in the conversion results. These errors are due

to feedthrough from the microprocessor to the successive

approximation comparator. The problem can be elimi-

nated by forcing the microprocessor into a wait state

during conversion or by using three-state buffers to iso-

late the ADC data bus.

DIGITAL INTERFACE

The A/D converter is designed to interface with micropro-

cessors as a memory mapped device. The CS and RD

control inputs are common to all peripheral memory

interfacing. A separate CONVST is used to initiate a con-

version.

Internal Clock

The A/D converter has an internal clock that eliminates the

need of synchronization between the external clock and

the CS and RD signals found in other ADCs. The internal

clock is factory trimmed to achieve a typical conversion

time of 0.65

µs and a maximum conversion time over the

full operating temperature range of 0.75

µs. No external

adjustments are required. The guaranteed maximum ac-

quisition time is 100ns. In addition, throughput time of

800ns and a minimum sampling rate of 1.25Msps is

guaranteed.

1410 F11

DIGITAL

SYSTEM

0.1

µF

ANALOG

INPUT

CIRCUITRY

0.1

µF

–

0.1

µF

+AIN

–AIN

AGND

REFCOMP

AVDD

VSS

DVDD DGND OGND

LTC1410

Figure 11. Power Supply Grounding Practice

LTC1410CSW bảng dữ liệu(PDF) 12 Page - Linear Technology

LTC1410CSW bảng dữ liệu(HTML) 12 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

bảng dữ liệu tải về

Link URL