LTC1288CS8 datasheet(13/24 Pages) LINER

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LTC1285/LTC1288

APPLICATION INFORMATION

Transfer Curve

The LTC1285/LTC1288 are permanently configured for

unipolar only. The input span and code assignment for

this conversion type are shown in the following figures.

VREF

4096

VIN

0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 0

•

LTC1285/88 • AI04

1LSB =

Transfer Curve

OUTPUT CODE

•

1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0

INPUT VOLTAGE

VREF – 1LSB

VREF – 2LSB

•

1LSB

INPUT VOLTAGE

(VREF = 5.000V)

4.99878V

4.99756V

•

0.00122V

LTC1285/88 • AI05

Output Code

Operation with DIN and DOUT Tied Together

The LTC1288 can be operated with DIN and DOUT tied

together. This eliminates one of the lines required to

communicate to the microprocessor (MPU). Data is trans-

mitted in both directions on a single wire. The processor

pin connected to this data line should be configurable as

either an input or an output. The LTC1288 will take control

of the data line and drive it low on the 4th falling CLK edge

after the start bit is received (see Figure 3). Therefore the

processor port line must be switched to an input before

this happens to avoid a conflict.

In the Typical Applications section, there is an example of

interfacing the LTC1288 with DINand DOUT tied together to

the Intel 8051 MPU.

ACHIEVING MICROPOWER PERFORMANCE

With typical operating currents of 160

µA and automatic

shutdown between conversions, the LTC1285/LTC1288

achieves extremely low power consumption over a wide

range of sample rates (see Figure 4). The auto-shutdown

allows the supply curve to drop with reduced sample rate.

Figure 3. LTC1288 Operation with DIN and DOUT Tied Together

CLK

DATA

(DIN/DOUT)

START

SGL/DIFF

ODD/SIGN

MSBF

B11

B10

•••

MSBF BIT LATCHED

BY LTC1288

LTC1288 CONTROLS DATA LINE AND SENDS

A/D RESULT BACK TO MPU

MPU CONTROLS DATA LINE AND SENDS

MUX ADDRESS TO LTC1288

PROCESSOR MUST RELEASE DATA LINE AFTER

4TH RISING CLK AND BEFORE THE 4TH FALLING CLK

LTC1288 TAKES CONTROL OF DATA LINE

ON 4TH FALLING CLK

LTC1285/88 F03

SAMPLE FREQUENCY (kHz)

0.1

100

1000

100

LTC1285/88 • F04

TA = 25°C

VCC = 2.7V

VREF = 2.5V

fCLK = 120kHz

Figure 4. Automatic Power Shutdown Between Conversions

Allows Power Consumption to Drop with Sample Rate

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