công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

UPD75P0116CU bảng dữ liệu(PDF) 39 Page - NEC

tên linh kiện UPD75P0116CU
Giải thích chi tiết về linh kiện  4-BIT SINGLE-CHIP MICROCONTROLLER
PDF  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  NEC [NEC]
Trang chủ  http://www.nec.com/
Logo NEC - NEC

UPD75P0116CU bảng dữ liệu(HTML) 39 Page - NEC

Back Button UPD75P0116CU Datasheet HTML 35Page - NEC UPD75P0116CU Datasheet HTML 36Page - NEC UPD75P0116CU Datasheet HTML 37Page - NEC UPD75P0116CU Datasheet HTML 38Page - NEC UPD75P0116CU Datasheet HTML 39Page - NEC UPD75P0116CU Datasheet HTML 40Page - NEC UPD75P0116CU Datasheet HTML 41Page - NEC UPD75P0116CU Datasheet HTML 42Page - NEC UPD75P0116CU Datasheet HTML 43Page - NEC Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 62 page
background image
µPD75P0116
39
SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY3
VDD = 2.7 to 5.5 V
1300
ns
3800
ns
SCK high-, low-level widths
tKL3
VDD = 2.7 to 5.5 V
tKCY3/2–50
ns
tKH3
tKCY3/2–150
ns
SB0, 1 setup time
tSIK3
VDD = 2.7 to 5.5 V
150
ns
(vs. SCK
↑)
500
ns
SB0, 1 hold time (vs. SCK
↑)tKSI3
tKCY3/2
ns
SCK
↓ → SB0, 1 output
tKSO3
RL = 1 k
Ω Note
VDD = 2.7 to 5.5 V
0
250
ns
delay time
CL = 100 pF
0
1000
ns
SCK
↑ → SB0, 1 ↓
tKSB
tKCY3
ns
SB0, 1
↓ → SCK ↓
tSBK
tKCY3
ns
SB0, 1 low-level width
tSBL
tKCY3
ns
SB0, 1 high-level width
tSBH
tKCY3
ns
Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.
SBI mode (SCK ··· external clock input (slave)): (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY4
VDD = 2.7 to 5.5 V
800
ns
3200
ns
SCK high-, low-level widths
tKL4
VDD = 2.7 to 5.5 V
400
ns
tKH4
1600
ns
SB0, 1 setup time
tSIK4
VDD = 2.7 to 5.5 V
100
ns
(vs. SCK
↑)
150
ns
SB0, 1 hold time (vs. SCK
↑)tKSI4
tKCY4/2
ns
SCK
↓ → SB0, 1 output
tKSO4
RL = 1 k
Ω Note
VDD = 2.7 to 5.5 V
0
300
ns
delay time
CL = 100 pF
0
1000
ns
SCK
↑ → SB0, 1 ↓
tKSB
tKCY4
ns
SB0, 1
↓ → SCK ↓
tSBK
tKCY4
ns
SB0, 1 low-level width
tSBL
tKCY4
ns
SB0, 1 high-level width
tSBH
tKCY4
ns
Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com