LTC1100ACS datasheet(6/8 Pages) LINER

6 / 8 page

LTC1100

HARA TERISTICS

TYPICALPERFOR

Large-Signal Transient Response

Small-Signal Transient Response

Overload Recovery

G = 100, VS = ±5V

8-Pin DIP (16-Pin SO)

Pin 1 (2) GND REF: Connect to system ground. This sets

the zero reference for the internal op amps.

Pin 2 (4) CMRR: This pin tailors the gain of the internal

amplifiers to maximize AC CMRR. For applications which

emphasize CMRR requirements, connect a 100k resistor

and a 10pF capacitor in series from CMRR to ground. See

the Applications section.

Pin 3 (6) –VIN: Inverting Input.

Pin 4 (7) V– : Negative Supply.

Pin 5 (10) V+: Positive Supply.

Pin 6 (11) VIN: Noninverting Input.

Pin 7 (13) COMP: This pin reduces the bandwidth of the

internal amplifiers for applications at or near DC. Clock

feedthrough from the internal sampling clock can also be

suppressed by using the COMP pin. The standard com-

pensation circuit is a capacitor from COMP to VOUT, sized

to provide an RC pole with the internal 247k resistor

(22.5k for LTC1100CS in gain-of-10 mode). See the

Applications section.

Pin 8 (15) VOUT: Signal Output.

16-Pin SO Package Only

(3) G = 10: Short to pin (2) for gain of 10. Leave

disconnected for gain of 100.

(14) G = 10: Short to pin (15) for gain of 10. Leave

disconnected for gain of 100.

NOTE:

Both pins must be shorted or open to provide

correct gain.

(1),(5),(8),(9),(12),(16) NC: No Internal Connection.

Large-Signal Transient Response

Small-Signal Transient Response

Overload Recovery

G = 10 (LTC1100CS Only), VS = ±5V

µs/DIV

LTC1100 • TPC18

LTC1100 • TPC16

µs/DIV

2V/DIV

µs/DIV

LTC1100 • TPC17

50ms/DIV

µs/DIV

LTC1100 • TPC13

µs/DIV

LTC1100 • TPC14

µs/DIV

LTC1100 • TPC15

1V/DIV

2V/DIV

50mV/DIV

2V/DIV

1V/DIV

PIN FUNCTIONS

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