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LT1777CS bảng dữ liệu(PDF) 16 Page - Linear Technology |
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LT1777CS bảng dữ liệu(HTML) 16 Page - Linear Technology |
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16 / 24 page ![]() 16 LT1777 As an example, assume that the capacitance between the VSW node and a high impedance pin node is 0.1pF, and that the high impedance node in question exhibits a capaci- tance of 1pF to ground. Also assume a “typical” 36VIN to 5VOUT application. Due to the large voltage excursion at the VSW node, this will couple a 3.5V(!) transient to the high impedance pin, causing abnormal operation. An explicit 100pF capacitor added to the node will reduce the amplitude of the disturbance to more like 35mV (although settling time will increase). APPLICATIONS INFORMATION Specific pin recommendations are as follows: SHDN: If unused, add a 100pF capacitor to ground. SYNC: Ground if unused. VC: Add a capacitor directly to ground in addition to the explicit compensation network. A value of one-tenth of the main compensation capacitor is recommended, up to a maximum of 100pF. FB: Assuming the VC pin is handled properly, this pin usually requires no explicit capacitor of its own, but keep this node physically small to minimize stray capacitance. |
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