LT1719CS6 datasheet(12/16 Pages) LINER

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LT1719

APPLICATIONS INFORMATION

Figure 7. LT1719 Block Diagram

–

+IN

–IN

AV1

VCC

VEE

SHUTDOWN

AV2

NONLINEAR STAGE

OUT

GND

1719 F07

+VS

BIAS CONTOL

Speed Limits

The LT1719 comparator is intended for high speed appli-

cations, where it is important to understand a few limita-

tions. These limitations can roughly be divided into three

categories: input speed limits, output speed limits, and

internal speed limits.

There are no signiﬁcant input speed limits except the

shunt capacitance of the input nodes. If the 2pF typical

input nodes are driven, the LT1719 will respond.

The output speed is constrained by two mechanisms, the

first of which is the slew currents available from the output

transistors. To maintain low power quiescent operation,

the LT1719 output transistors are sized to deliver 35mA to

60mA typical slew currents. This is sufﬁcient to drive small

capacitive loads and logic gate inputs at extremely high

speeds. But the slew rate will slow dramatically with heavy

capacitive loads. Because the propagation delay (tPD)

deﬁnition ends at the time the output voltage is halfway

between the supplies, the ﬁxed slew current makes the

LT1719 faster at 3V than 5V with large capacitive loads and

sufficient input overdrive.

Another manifestation of this output speed limit is skew,

the difference between tPD+ and tPD–. The slew currents of

the LT1719 vary with the process variations of the PNP

and NPN transistors, for rising edges and falling edges

respectively. The typical 0.5ns skew can have either polar-

ity, rising edge or falling edge faster. Again, the skew will

increase dramatically with heavy capacitive loads.

common mode range. The differential input voltage range

is rail-to-rail, without the large input currents found in

competing devices. The input stage also features phase

reversal protection to prevent false outputs when the

inputs are driven below the –100mV common mode

voltage limit.

The internal hysteresis is implemented by positive, nonlin-

ear feedback around a second gain stage. Until this point,

the signal path has been entirely differential. The signal

path is then split into two drive signals for the upper and

lower output transistors. The output transistors are con-

nected common emitter for rail-to-rail output operation.

The Schottky clamps limit the output voltages at about

300mV from the rail, not quite the 50mV or 15mV of Linear

Technology’s rail-to-rail ampliﬁers and other products.

But the output of a comparator is digital, and this output

stage can drive TTL or CMOS directly. It can also drive ECL,

as described earlier, or analog loads as demonstrated in

the applications to follow.

The bias conditions and signal swings in the output stage

are designed to turn their respective output transistors off

faster than on. This helps minimize the surge of current

from + VS to ground that occurs at transitions, to minimize

the frequency-dependent increase in power consumption.

The frequency dependence of the supply current is shown

in the Typical Performance Characteristics.

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