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LT1373CS8 bảng dữ liệu(PDF) 10 Page - Linear Technology |
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LT1373CS8 bảng dữ liệu(HTML) 10 Page - Linear Technology |
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10 / 12 page ![]() 10 LT1373 VRIPPLE = output ripple (VP-P) gm = error amplifier transconductance (≈ 375µmho) RC = series resistor on VC pin VOUT = DC output voltage To prevent irregular switching, VC pin ripple should be kept below 50mVP-P. Worst-case VC pin ripple occurs at maximum output load current and will also be increased if poor quality (high ESR) output capacitors are used. The addition of a 0.001 µF capacitor on the VC pin reduces switching frequency ripple to only a few millivolts. A low value for RC will also reduce VC pin ripple, but loop phase margin may be inadequate. Switch Node Considerations For maximum efficiency, switch rise and fall time are made as short as possible. To prevent radiation and high fre- quency resonance problems, proper layout of the compo- nents connected to the switch node is essential. B field (magnetic) radiation is minimized by keeping output di- ode, switch pin and output bypass capacitor leads as short as possible. E field radiation is kept low by minimizing the length and area of all traces connected to the switch pin. A ground plane should always be used under the switcher circuitry to prevent interplane coupling. Positive-to-Negative Converter with Direct Feedback LT1373 VIN VC VIN 2.7V TO 16V 1 3 †MAX IOUT 8 5 4 6, 7 *COILTRONICS CTX20-2 (407) 241-7876 GND NFB LT1373 • TA03 VSW S/S D2 P6KE-15A D3 1N4148 D1 MBRS130LT3 C1 22 µF C2 0.01 µF R1 5k R3 2.49k 1% R2 2.55k 1% –VOUT † –5V C3 47 µF ON OFF VIN 3V 5V 9V IOUT 0.3A 0.5A 0.75A 2 1 4 T1* 3 • • + + Dual Output Flyback Converter with Overvoltage Protection LT1373 VIN FB VC VIN 4.75V TO 13V 1 3 8 5 2 4 6, 7 *DALE LPE-4841-100MB (605) 665-9301 GND NFB LT1373 • TA04 VSW S/S P6KE-20A 1N4148 MBRS140T3 MBRS140T3 C1 100 µF R2 275k 1% R1 302.6k 1% C2 0.01 µF R3 5k R5 2.49k 1% R4 12.4k 1% –VOUT –15V VOUT 15V C3 47 µF C4 47 µF ON OFF 2, 3 6, 7 5 T1* 4 8 1 • • • + + + TYPICAL APPLICATIONS N The high speed switching current path is shown schemati- cally in Figure 3. Minimum lead length in this path is essential to ensure clean switching and low EMI. The path including the switch, output diode and output capacitor is the only one containing nanosecond rise and fall times. Keep this path as short as possible. More Help For more detailed information on switching regulator circuits, please see AN19. Linear Technology also offers a computer software program, SwitcherCAD TM, to assist in designing switching converters. In addition, our applica- tions department is always ready to lend a helping hand. LOAD VOUT L1 SWITCH NODE LT1373 • F03 VIN HIGH FREQUENCY CIRCULATING PATH Figure 3 APPLICATIO S I FOR ATIO SwitcherCAD is a trademark of Linear Technology Corporation. |
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