LT1339C datasheet(8/20 Pages) LINER

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LT1339

FUNCTIONAL BLOCK DIAGRA

OPERATION

Basic Control Loop

The LT1339 uses a constant frequency, current mode

synchronous architecture. The timing of the IC is provided

through an internal oscillator circuit, which can be syn-

chronized to an external clock, programmable to operate

at frequencies up to 150kHz. The oscillator creates a

modified sawtooth wave at its timing node (CT) with a slow

charge, rapid discharge characteristic.

During typical positive buck operation, the main switch

MOSFET is enabled at the start of each oscillator cycle. The

main switch stays enabled until the current through the

switched inductor, sensed via the voltage across a series

(Refer to Functional Block Diagram)

sense resistor (RSENSE), is sufficient to trip the current

comparator (IC1) and, in turn, reset the RS latch. When the

RS latch resets, the main switch is disabled, and the

synchronous switch MOSFET is enabled. Shoot-through

prevention logic prohibits enabling of the synchronous

switch until the main switch is fully disabled. If the current

comparator threshold is not obtained throughout the

entire oscillator charge period, the RS latch is bypassed

and the main switch is disabled during the oscillator

discharge time. This “minimum off time” assures ad-

equate charging of the bootstrap supply, protects the main

switch, and is typically about 1

µs.

–

1.25V

SOFT START

µA

IAVG

–

1.25V

REFERENCE

VFB

0.5

µA

× 15

CURRENT

SENSE AMP

IC1

OSC

SL/ADJ

NONOVERLAPPING

SWITCH LOGIC

UVLO

CIRCUIT

VBOOST

PHASE

12VIN

SENSE+

VIN

5VREF

MAIN

SWITCH

SYNC

SWITCH

SENSE–

RSENSE

VOUT

1339 • BD

CIRCUIT

ENABLE

–

2.5V

PGND

SGND

ONE SHOT

50k

AVERAGE

CURRENT

LIMIT

RUN/SHDN

5VREF

VREF

SYNC

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