LT1161CS datasheet(7/12 Pages) LINER

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LT1161

spike can play havoc with the power supply and false trip

the current-sense comparator.

Turn-on

∂V/∂t is controlled by the addition of the simple

network shown in Figure 6. This network takes advantage

of the fact that the MOSFET acts as a source follower

during turn-on. Thus the

∂V/∂t on the source can be

controlled by controlling the

∂V/∂t on the gate:

∂

−

where VTH is the MOSFET gate threshold voltage. Multiply-

ing CLOAD times this ∂V/∂t yields the value of the current

spike. For example, if V+ = 24V, VTH = 2V, and C1 = 0.1µF,

∂V/∂t = 2.2V/ms, resulting in a 2.2A turn-on spike into

1000

µF. The diode and second resistor in the network

ensure fast current limit turn-off.

When turning off a capacitive load, the source of the

MOSFET can “hang up” if the load resistance does not

discharge CLOAD as fast as the gate is being pulled down.

If this is the case, a diode may have to be added from

source to gate to prevent VGS(MAX) from being exceeded.

and CD delay the overcurrent trip for drain currents up to

approximately 10

× ISET, above which the diode conducts

and provides immediate turn-off (see Figure 7).

To ensure

proper operation of the timer, CD must be ≤ CT.

MOSFET DRAIN CURRENT (1 = SET CURRENT)

0.1

0.01

100

L1161 F07

Printed Circuit Board Shunts

The sheet resistance of 1oz. copper clad is approximately

× 10–4Ω/square with a temperature coefficient of

+0.39%/

°C. Since the LT1161 drain sense threshold has a

similar temperature coefficient (+0.33%/

°C), this offers

the possibility of nearly zero TC current sensing using

“free” drain sense resistors made out of PC trace material.

A conservative approach is to use 0.02" of width for each

1A of current for 1oz. copper. Combining the LT1161 drain

sense threshold with the 1oz. copper sheet resistance

results in a simple expression for width and length:

Width (1oz. Cu) = 0.02"

× ISET

Length (1oz. Cu) = 2"

The width for 2oz. copper would be halved while the length

would remain the same.

Bends may be incorporated into the resistor to reduce

space; each bend is equivalent to approximately 0.6

width of straight length. Kelvin connections should be

employed by running separate traces from the ends of the

resistors back to the LT1161 V+ and sense pins. See

Application Note 53 for further information on printed

circuit board shunts.

Adding Current Limit Delay

When capacitive loads are being switched or in very noisy

environments, it is desirable to add delay in the drain

current-sense path to prevent false tripping (inductive

loads normally do not need delay). This is accomplished

by the current limit delay network shown in Figure 6. RD

LT1161

24V

V+

1161 F06

RD (≤10k)

1RFZ24

CLOAD

CURRENT LIMIT

DELAY NETWORK

∂V/∂t CONTROL NETWORK

1N4148

100k

Figure 6.

∂V/∂t Control and Current Limit Delay

Figure 7. Current Limit Delay Time

APPLICATIONS INFORMATION

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