UPD750104 datasheet(13/80 Pages) NEC

13 / 80 page

µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)

Input state

: To be connected to VSS or VDD

through a separate resistor

Output state : To be left open

Input state

: To be connected to VSS or VDD

through a separate resistor

Output state : To be left open

Input state

: To be connected to VSS

Output state : To be connected to VSS

(Do not connect to a pull-up

resistor specified with a mask

option.)

3.4

Connection of Unused Pins

Table 3-1. Connection of Unused Pins

Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-

in feedback resistor).

Pin name

Recommended connection

P00/INT4

To be connected to VSS or VDD

P01/SCK

P02/SO/SB0

P03/SI/SB1

To be connected to VSS

P10/INT0 - P12/INT2

To be connected to VSS or VDD

P13/TI0

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

P30 - P33

P40 - P43

P50 - P53

P60/KR0 - P63/KR3

P70/KR4 - P73/KR7

P80, P81

XT1Note

To be connected to VSS or VDD

XT2Note

To be left open

To be connected directly to VDD

To be connected to VSS or VDD through a

separate resistor

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