Peripheral migration

AN4617

14/26

DocID027161 Rev 1

Note:

Recent products can feature additional DMA channels corresponding to the added

peripherals. User has to refer to the latest available documentation.

2.6

Interrupt vectors

Table 9 summarizes the differences of the interrupt vector table between the STM32F0 and

STM32L0 series.

Table 8. DMA request differences between STM32F0 and STM32L0 series

Peripheral

STM32F0 series

STM32L0 series

USART3

USART4

USART5

LPUART1

Ch2, Ch3, Ch6, Ch7

Ch6, Ch7

Ch1, Ch2, Ch3, Ch4, Ch5, Ch6, Ch7

Not available

Not available

Ch2, Ch3, Ch6, Ch7

Ch2, Ch3, Ch6, Ch7

Ch2, Ch3, Ch6, Ch7

TIM1

TIM3

TIM6

TIM15

TIM16

TIM17

Ch2, Ch3, Ch4, Ch5, Ch7

Ch2, Ch3, Ch4, Ch6

Ch3

Ch5

Ch3, Ch4, Ch6

Ch1, Ch2, Ch7

Not available

Ch2, Ch3, Ch5, Ch6

Ch2

Not available

Not available

Not available

DAC

Ch3, Ch4

Ch2, Ch4

AES

Not available

Ch1, Ch2, Ch3, Ch5

Table 9. Interrupt vector differences between STM32F0 and STM32L0 series

Position [Priority]

STM32F0 series

STM32L0 series

- [0]

Reserved

Memory management

- [1]

Reserved

Pre-fetch fault, memory access fault

- [2]

Reserved

Undefined instruction or illegal state

- [4]

Reserved

Debug Monitor

1 [8]

EXTI lines 16 and 31

PVD comparator through EXTI Line

3 [10]

Flash

Flash and EEPROM

10 [17]

DMA1_CH2_3, DMA2_CH1_2

DMA1_CH2_3

11 [18]

DMA1_CH4_5_6_7, DMA2_CH3_4_5

DMA1_CH4_5_6_7

13 [20]

TIM1 break, update, trigger and commutation

LPTIM1 through EXTI29

14 [21]

TIM1 capture compare

Reserved

19 [26]

TIM14

Reserved

20 [27]

TIM15

TIM21

21 [28]

TIM16

I2C3