2

µPD72107

BLOCK DIAGRAM

Name

Function

Bus interface

An interface between the

µPD72107 and external memory or external host processor

Internal controller

Manages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block

DMAC

Controls the transfer of data on the external memory to the internal controller or transmitter block,

(Direct Memory

and controls the writing of data in the internal controller or receiver block to the external memory

Access Controller)

TxFIFO

A 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block

RxFIFO

A 32-byte buffer for when receive data is sent from the receiver block to the DMAC

Transmitter

Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data

Receiver

Receives HDLC frame and writes internal data to RxFIFO

Internal bus

An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block,

and bus interface block

D0-D7

A16D8

-A23D15

A0-A15

IORD

IOWR

MRD

MWR

UBE

CS

ASTB

AEN

READY

HLDRQ

HLDAK

CRQ

INT

CLRINT

B/W

PU

GND

RESET

CLK

Bus

interface

Internal controller

TxFIFO

Transmitter

Internal bus

Receiver

RxFIFO

DMAC

TxC

TxD

RTS

CTS

CD

RxC

RxD