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TN0941 bảng dữ liệu(PDF) 11 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  When to and why use reset and supervisor ICs
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TN0941
What are the following additional options of reset and supervisor ICs used for?
16
6.4
Chip enable gating
Internal gating of the memory chip enable signal (E) prevents erroneous data from
corrupting the external SRAM in the event of an undervoltage condition. The chip enable
signal, which normally goes directly from the microcontroller to the SRAM, is routed instead
through the supervisor device. The short propagation delay enables the chip enable gating
to be used with most microcontrollers. During normal operation (reset not asserted), the
transmission gate is enabled and passes all E transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from corrupting the SRAM.
More details
See AN1957: Microprocessor Supervisor Functions, page 17
Suggested products
For further information on chip enable gating signals, please refer to STM795 and STM818.
6.5
Early power failure
Inadvertent or unexpected power loss can cause a number of malfunctions in a system
(example, data loss, uncontrolled program status, and indeterminate processor state). For a
reliable design, systems should receive early power failure warnings, to leave enough time
for the microprocessor to start a safeguard routine, for backing up crucial data (example,
registers). Hence, power fail comparators are used to monitor unregulated or failing power
supplies through a voltage divider. Their reaction to power loss is very fast, and can provide
enough time to execute all the necessary safeguard processes that precede an expected
power failure.
More details
•
See AN1957: Microprocessor Supervisor Functions, page 18
•
See AN1336: Power-Fail Comparator for NVRAM Supervisory Devices
Suggested products
For further information on early power failures, please refer to the following products
on:
STM69x, STM70x, STM80x, STM81x, and STM1404.
Design tip
The power fail comparator input may be connected to a manual reset so that an early low
voltage condition generates a reset output.



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