3.3

System timers

This sub-section describes the System Timers peripherals (WDG, SLPTMR, MACTMR) bits and registers migration from revision

13 to revision 14 of the STM32W108xx datasheet.

3.3.1

STM32W108xx watchdog timer overview

There are no major updates on the WDG IP. The only updates are related to the bit and register naming.Table 7 gives the list of the

changes made in the WDG bits and registers naming.

3.3.2

STM32W108xx Sleep timer Overview

The sleep Timer IP has two levels of changes: the first one is related to the IP structure and to the low power modes requirement

and the second one is related to the bits and registers naming.

●

The sleep timer force register SLPTMR_IFR is required in low power modes: if the dedicated sleep timer interrupt (WRAP,

CMPA or CMPB) is enabled and configured as wake event, in this case the interrupt will not be generated when the CPU

Table 7.

WDG bits and registers overview

Offset

Register

STM32W108xx WDG bits/registers naming overview

0x6000

WDOG_CFG

Reserved

WDOG_DIS

WDOG_EN

WDG_CR

Reserved

WDGDIS

WDGEN

0x6004

WDOG_CTRL

Reserved

WDOG_CTRL

WDG_KR

Reserved

KEY[15:0]

0x6008

WDOG_RESTART

Reserved

WDOG_RESTART

WDG_KICKSR

Reserved

KS[15:0]