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AN4013 bảng dữ liệu(PDF) 19 Page - STMicroelectronics

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AN4013 bảng dữ liệu(HTML) 19 Page - STMicroelectronics

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AN4013
General-purpose timer modes
36
To configure the timer in this mode:
1.
Configure the output pin:
a)
Select the output mode by writing CCS bits in CCMRx register.
b)
Select the polarity by writing the CCxP bit in CCER register.
2.
Select the Combined PWM mode (Combined PWM1 or Combined PWM2) by writing
OCxM bits in CCMRx register.
3.
Program the period, the delay and the phase shift respectively in ARR, CCRx and
CCRy registers.
4.
Select the counting mode:
a)
Edge-aligned mode: the counter must be configured up-counting or down-
counting.
b)
Center aligned mode: the counter mode must be center aligned counting mode
(CMS bits different from '00')
5.
Enable the capture compare.
6.
Enable the counter.
2.9
Retriggerable one pulse mode available for
STM32F30x and STM32F3x8
The Retriggerable one pulse mode is a one pulse mode with the particularity of:
The pulse starts as soon as the trigger occurs (no programmable delay)
The pulse is extended if a new trigger occurs before the previous one is completed
If the counter is configured in up-counting mode, the corresponding CCRx must be set to 0,
in this case the pulse length is determined by ARR register. If the timer is configured in
down-counting mode, the ARR must be set to 0 in this case the pulse length is determined
by CCRx register. As for the OPM mode, there are two Retriggerable one pulse mode,
Retriggerable OPM mode 1 and Retriggerable OPM mode 2:
Retriggerable OPM mode 1 is selected by setting the OCXM bits to 1000:
–
In up-counting mode, channel is inactive until a trigger event is detected (on TRGI
signal), the comparison is performed like in PWM mode 1, then the channel
becomes inactive again at the next update.
–
In down-counting mode, channel is active until a trigger event is detected (on
TRGI signal), the comparison is performed like in PWM mode 1, then the channel
becomes active again at the next update.
Retriggerable OPM mode 2 i s selected by setting the OCXM bits to 1001:
–
In up-counting mode, the channel is active until a trigger event is detected (on
TRGI signal), the comparison is performed like in PWM mode 2, then the channel
becomes inactive again at the next update.
–
In down-counting mode, the channel is inactive until a trigger event is detected (on
TRGI signal), the comparison is performed like in PWM mode 1, then the channel
becomes inactive again at the next update.



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