M24xxx EEPROM: 400 kHz and 1 MHz clock

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M24xxx EEPROM: 400 kHz and 1 MHz clock

1.1

M24xxx 400 kHz AC tables until 2007

In the last revisions of the I²C-bus specification, defined by NXP/Philips, one can see that

the 1 MHz serial clock rate was introduced in 2007:

•

January 2000: the I²C-bus specification defines a clock rate of either 100 kHz, 400 kHz

•

June 2007: the I²C-bus specification defines a new table offering all timings related to

the 1 MHz clock.

Before 2007, the M24xxx EEPROM devices offered by ST were specified with an AC table

based on a 400 kHz (max) clock rate.

Two main differences appear when comparing the 400 kHz M24xxx AC table with the I²C-

bus specification AC table (see Table 2):

•

•

Why such differences?

The M24xxx devices are designed to offer the best performances compatible with the I²C-

bus specification, that is:

•

serial clock SCL: time for the data line SDA to hold the previous bit value before changing

state). This min value pushes away the SDA change from the SCL falling edge: that is a

safe timing condition, as SDA and SCL must never switch at the same time (such an event

is a critical event for the I²C-bus, as it could be randomly decoded as either a Start, a Stop or

a Data-in event).

•

a. The 3.4 MHz clock rate is not supported by the M24xxx EEPROM.

Table 2. Access time and Noise filter parameters specified in the 400 kHz AC table

Symbol

Alt

Parameter

M24xxx

Unit

Min

Max

Min

Max

Data valid time

-

900

-

900

ns

100

-

0

-

ns

Pulse width ignored (input filter on SCL and

SDA)

-

50 (or

more)

050

ns