Die description

TN0193

2/6

Doc ID 17034 Rev 3

1

Die description

For details on the device operation, as well as for electrical and functional characteristics,

please refer to the LRIS64K datasheet available from your STMicroelectronics sales office.

Pad extraction

All pad placements are referred to the center of the chip. All dimensions are given in

microns.

Table 1.

Pad placements

1.

Refer to Figure 1 for an illustration.

Signal name

X

Y

1

2.

Pad passivated on sawn and bumped wafers.

–550

744.31

2DU(2)

–355.14

744.31

3DU(2)

355

744.31

4DU(2)

550

744.31

5DU(2)

642

–717.02

6DU(2)

542

–892

3.

Pad bumped on sawn and bumped wafers.

357.94

–725.57

8AC0(3)

–332.06

–725.57

9DU(2)

–640

–800

10

NC (not connected internally)(3)

–65.81

158.77