PM0063 datasheet(12/30 Pages) STMICROELECTRONICS

12 / 30 page

Reading/programming the STM32F100xx embedded Flash memory

PM0063

12/30

Doc ID 16211 Rev 2

In case of non-availability of a high frequency clock in the system, Flash memory accesses

can be made on a half cycle of HCLK (AHB clock), the frequency of HCLK permitting (half-

cycle access can only be used with a low-frequency clock of less than 8 MHz that can be

obtained with the use of HSI or HSE but not of PLL). This mode can be chosen by setting a

control bit in the Flash access control register.

Note:

Half-cycle access cannot be used when there is a prescaler different from 1 on the AHB

clock.

2.2.2

D-Code interface

The D-Code interface consists of a simple AHB interface on the CPU side and a request

generator to the Arbiter of the Flash access controller. D-code accesses have priority over

prefetch accesses.

2.2.3

Flash access controller

Mainly, this block is a simple arbiter between the read requests of the I-code and D-Code

interfaces.

D-Code interface requests have priority over I-Code requests.

2.3

Flash program and erase controller (FPEC)

The FPEC block handles the program and erase operations of the Flash memory. The

FPEC consists of seven 32-bit registers.

●

FPEC key register (FLASH_KEYR)

●

Option byte key register (FLASH_OPTKEYR)

●

Flash control register (FLASH_CR)

●

Flash status register (FLASH_SR)

●

Flash address register (FLASH_AR)

●

Option byte register (FLASH_OBR)

●

Write protection register (FLASH_WRPR)

An ongoing Flash memory operation will not block the CPU as long as the CPU does not

access the Flash memory.

2.3.1

Key values

The key values are as follows:

●

RDPRT key = 0x00A5

●

KEY1 = 0x45670123

●

KEY2 = 0xCDEF89AB

2.3.2

Unlocking the Flash memory

After reset, the FPEC block is protected. The FLASH_CR register is not accessible in write

mode. An unlocking sequence should be written to the FLASH_KEYR register to open up

the FPEC block. This sequence consists of two write cycles, where two key values (KEY1

and KEY2) are written to the FLASH_KEYR address (refer to Section 2.3.1 for key values).

Any wrong sequence locks up the FPEC block and FLASH_CR register until the next reset.

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