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AN2628 bảng dữ liệu(PDF) 16 Page - STMicroelectronics |
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AN2628 bảng dữ liệu(HTML) 16 Page - STMicroelectronics |
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16 / 27 page ![]() Register description AN2628 16/27 FL.5 Interrupt flag 5: XASC transmit buffer ‘0’: No interrupt request. ‘1’: Interrupt request pending. FL.6 Interrupt flag 6: XASC transmit ‘0’: No interrupt request. ‘1’: Interrupt request pending. FL.7 Interrupt flag 7: XASC receive ‘0’: No interrupt request. ‘1’: Interrupt request pending. IE.0 Interrupt enable 0: CAN1 interrupt ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. IE.1 Interrupt enable 1: I2C transmit ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. IE.2 Interrupt enable 2: I2C receive ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. IE.3 Interrupt enable 3: XSSC transmit ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. IE.4 Interrupt enable 4: XSSC receive ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. IE.5 Interrupt enable 5: XASC transmit buffer ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. IE.6 Interrupt enable 6: XASC transmit ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. IE.7 Interrupt enable 7: XASC receive ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. Table 1. XIR0SEL register (continued) Bit Function |
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