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UPD6708 bảng dữ liệu(PDF) 23 Page - NEC |
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UPD6708 bảng dữ liệu(HTML) 23 Page - NEC |
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23 / 72 page ![]() 23 µPD6708 4.1.4 Status register (STR) STR is an 8-bit register used to determine the status of the µPD6708. The statuses of WDB and RDB and the status of interrupts can be read from higher 4 bits. The return code, which indicates the result of the communication, can be read from lower 4 bits. Table 4-2. Contents of Status Register Bit Value Meaning Description Bit 7 1 WDB is full Indicates whether data can be written to WDB 0 WDB is not full Bit 6 1 RDB is empty Indicates whether data can be read from RDB 0 RDB is not empty Bit 5 1 WDB is empty Indicates whether data is in WDB 0 WDB is not empty Bit 4 1 Interrupt requested Indicates whether interrupt servicing is being requested (Bit 4 of the status 0 Interrupt not requested register is reset by STR by the host controller) Bit 3 to Return code Return code will be read Bit 0 4.2 Host Interface Modes The host controller can access WDB, RDB, CMR, and STR within the µPD6708 via the serial interface (SCK, SI, SO). There are four modes for accessing the serial interface, as shown in the Table 4-3. There are two method for switching among these four host interface modes: by using C/D pin and R/W pin, and by writing data to CMR (software control). Table 4-3. Host Interface Mode Mode Operation Data write mode Data input to SI pin is written to WDB from MSB at the rising edge of the serial clock input to SCK pin. Data setting is completed at the eighth serial clock cycle. Data read mode RDB data is output from MSB to SO pin at the falling edge of the serial clock input to SCK pin. A data read is completed by inputting eight serial clock cycles. Data at SI pin is ignored. Command write mode Data input to SI pin is written to CMR from MSB at rising edge of the serial clock input to SCK pin. Data setting is completed at the eight serial clock cycle. Status read mode STR data is output from MSB to SO pin at the falling edge of the serial clock input to SCK pin. A data read is completed by inputting eight serial clock cycles. Data at SI pin is ignored. |
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