D6467 datasheet(21/68 Pages) NEC

21 / 68 page

µPD6467

Data Sheet S14455EJ1V0DS00

2.3 Power-ON Clear Function

Because the internal status of the IC is undefined on power application, execute power-ON clear by lowering the

PCL pin for the duration described below.

Command setting on power-ON clear is as follows:

•

Clears test mode

•

Default setting of initial status (Refer to 3.14 Initial Status Setting Command.)

•

Clears all character data (12 rows, 28 columns) of video RAM (Display Off Data (FEH)). No data blinks.

•

Video RAM write address (row 0, digit 0)

•

Standard size for all rows as character size (SV1, SV0, SH1, SH0) = (0, 0, 0, 0)

•

All rows specified for output pin selection (OD1, OD0) = (0, 0)

•

Display OFF, LC oscillation ON, blinking OFF

•

Display of each channel OFF

•

No background and framing for all three channels

•

Character color reversing OFF

•

Character left and right reverse OFF

•

Blue back OFF

•

Low-order (0) bank for character address

•

Output switch control is only SW1 = ON, others OFF (S3A, S3B, SW4, SW2, SW1) = (1, 0, 0, 0, 1)

The time required for power-ON clear can be calculated by the following expression. Do not input any command

during this time.

t (Time required for power-ON clearing) = tPCLLNote + Video RAM clear time

= 10 (

µs) + 10 (µs) + 12/fOSC (MHz) × 336

= 10 (

µs) + 10 (µs) + 24/fOSC2 (MHz) × 336

fOSC (MHz): LC oscillation frequency or external input clock frequency (when

×1 frequency mode

is selected)

fOSC2 (MHz): External input clock frequency (when

×2 frequency mode is selected)

Note

Refer to Power-ON Clear Specifications in 6. ELECTRICAL CHARACTERISTICS.

To clear the video RAM, the dot clock (OSCIN pin) must be input. Be sure to input the clock when the input of an

external clock is selected.

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