UPD6465CS datasheet(31/52 Pages) NEC

31 / 52 page

µPD6464A,6465

When VS is small, it is suited for horizontal sync. separation, but is against to vertical sync. separation. And

when VS is large, edge noise of horizontal sync. separation causes a synchronization error (jitter). Therefore,

the constant of each element in the circuit should be optimized according to input signal’s characteristics.

The C2 capacitance should be specified as a sufficient larger value compared to charge/discharge current.

If the value overly exceeds the suitable value, however, excessive response characteristics will be inferior,

falling to trace rapid average-picture-level (APL) fluctuation of input signal. In the circuit shown in Figure 5-1

(a), a capacitor is connected to the composite video signal input portion for measurement. However, this makes

it hard to trace APL fluctuation. Therefore, in designing an actual circuit, insert a sync-chip clamp in front of

Q1 in Figure 5-1 (a). to stabilizes the potential of a synchronization signal, for tracing APL fluctuation.

Caution

In the circuit of Figure 5-1 (a), the width of the Hsync synchronization signal that is included in

the composite synchronization signal after separation may be wider than that of the Hsync

synchronization signal that is included in the input video signal, because of its circuit configuration.

Therefore, the width of the Hsync synchronization signal during a command continuous input

enable time (refer to 3.5 BUSY Period for Command Input) should be the same as that of the Hsync

synchronization signal included in Csync after separation in the circuit of Figure 5-1 (a).

UPD6465CS bảng dữ liệu(PDF) 31 Page - NEC