UPD6462GS datasheet(22/60 Pages) NEC

22 / 60 page

µPD6461, 6462

3. COMMAND DETAILS

3.1 VIDEO RAM BATCH CLEAR COMMAND

This command clears the entire video RAM by means of a single operation (the bit configuration is the same as for MSB-

first and LSB-first transfer).

The video RAM batch clear command places the system in the following state:

•

All character data in video RAM (12 rows

× 24 columns) is cleared (to display-off data (FEH:

µPD6461/7EH:

µPD6462)) and blinking is turned off.

•

The video RAM write address is (row 0, column 0).

•

The character size is single (minimum) for all rows.

•

The output distribution format is set to the default (the VC1 and VC2 bits are set to 0).

•

Display is turned off and LC oscillation is turned on.

The time required for clearing video RAM is calculated as follows. No command must be input while the video RAM is

being cleared.

Time required to clear video RAM = 10(

µs) + 12/fOSC(MHz) × 288

fOSC(MHz) : LC oscillation frequency or external clock frequency

A dot clock input (to the OSCIN pin) is necessary to clear the video RAM. Input a dot clock when external clock input

is selected.

Remark Power-on clear using the PCL pin is hardware reset, initializing the IC, including clearing the video RAM and

releasing test mode. The video RAM batch clear command, in contrast, performs software reset by initializing

the IC without first releasing test mode.

(MSB)

(LSB)

00000000

UPD6462GS bảng dữ liệu(PDF) 22 Page - NEC