AN2339

Development and debugging tool support

13/20

The JTAG input signals have weak internal pull-up and pull-down resistors, but these are not

always active:

●

When debug protection is activated (JTAG permanently held in reset internally)

●

At power up and down there may be a short duration where the power on reset is

already released internally, but where the resistors are not yet active.

To avoid any floating input pins even for a very short period it is highly recommended to

always provide additional external pull-up and pull-down resistors. This recommendation is

valid whether the JTAG port is used or not.

RTCK

JRTCK

Return TCK (to

JTAG equipment)

The RTCK signal is returned by the core to the

JTAG equipment, and the clock is not

advanced until the core had captured the data.

In adaptive clocking mode, the debugging

equipment waits for an edge on RTCK before

changing TCK.

TDO

JTDO

Test data out (to

JTAG equipment)

TDO is the return path of the data input signal

TDI.

nSRST

nRSTIN

System reset

(bidirectional)

nSRST is an active LOW open-collector signal

that can be driven by the JTAG equipment to

reset the target board. Some JTAG equipment

senses this line to determine when a board has

been reset by the user.

When the signal is driven LOW by the reset

controller on the core module, the motherboard

resets the whole system by driving nSYSRST

low.

DBGRQ

GND

(not used)

Debug request

(from JTAG

equipment)

DBGRQ is a request for the processor core to

enter debug state.

DBGACK

GND

(not used)

Debug

acknowledge (to

JTAG equipment)

DBGACK indicates to the debugger that the

processor core has entered debug mode.

Table 1.

JTAG interface signals

Std name

STR91x

name

Direction/

Description

Function