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AN2197 bảng dữ liệu(PDF) 5 Page - STMicroelectronics

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AN2197 bảng dữ liệu(HTML) 5 Page - STMicroelectronics

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AN2187
3 Feature compatibility
5/13
3
Feature compatibility
3.1
Pinout
TQFP44 or TQFP32 pin packages in all salestypes are fully pin to pin compatible. ST72F325
devices have addtional alternate functions for the 8-bit PWMART and I2C (see <Blue HT>Table
4).
Table 4.
Addition of 8-bit PWMART and I2C Alternate Function I/Os
Note: PWM3-0 are the Pulse Width Modulation outputs and ARTCLK is the external clock for
the 8-bit Auto reload timer. SDAI is the serial data and SCLI is the serial clock pin for the I2C
peripheral. N/A stands for not-available.
3.2
VDD Rise time
Some timing differences exist between the products (see<Blue HT>Table 5). The application
must ensure that the power supply ramps up within the time window specified for the
microcontroller.
Table 5.
VDD Rise time
3.3
Asynchronous RESET pin
The VIL/VIH of reset pin has been changed to 0.3Vdd/0.7Vdd from 0.16Vdd/0.85Vdd
respectively (see <Blue HT>Table 6).
Table 6.
RESET Pin Characteristics
ST72F325 only
TQFP44
PWM3
(pin 2)
PWM2
(pin 3)
PWM1
(pin 4)
PWM0
(pin 5)
ARTCLK
(pin 6)
SDAI
(pin 36)
SCLI
(pin 37)
TQFP32
PWM3
(pin 28)
N/A
N/A
PWM0
(pin 29)
ARTCLK
(pin 30)
SDAI
(pin 18)
SCLI
(pin 19)
Symbol
Description
Device
Conditions
Min
Max
VtPOR
VDD rise time
ST72F324 / 324B
ST72F321B / 325
LVD enabled
6
µs/V
100ms/V
ST72F321
LVD enabled
6
µs/V
20ms/V
ST72F324, ST72F321
ST72F324B, ST72F321B, ST72F325
Min
Max
Min
Max
VIL
0.16xVDD
0.3xVDD
VIH
0.85xVDD
0.7xVDD



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