AN1636 datasheet(23/42 Pages) STMICROELECTRONICS

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UNDERSTANDING AND MINIMISING ADC CONVERSION ERRORS

The parasitic capacitance formed at the analog input because of track paths etc. appears in

parallel with external capacitance. So it must be added to CAIN. However when the parasitic

capacitance value is much less than CAIN, it can be ignored.

When CAIN is small (for example CAIN < 100*CADC ), it may not be able to hold the VIN voltage

effectively. So when ADC conversion is started, CADC will appear across the CAIN through

RADC causing CAIN to effectively discharge. So we need to consider the sampling time re-

quired with external resistance and capacitance.

Figure 20. RAIN Vs fADC

For example:

With RAIN=10K, CAIN (or Cparasitic) = 10pf, CADC=6pf

Time for charging external capacitor = RAIN*CAIN= 10k* 10pf = 100ns

10*RAIN*CAIN = 1us.

Time for charging hold capacitor CADC = (RAIN+RADC)* CADC

RC = 12K*6pf =72ns

10RC = 720ns = 0.72us

Total time = 1us + 0.72µs = 1.72µs. (approx.)

So, for ADCs with fADC=2Mhz, sampling time = 4*tAD= 2µs.

With total time of 1.72µs obtained with RAIN and Cparasitic, the sampling time of 2µs is already

at its upper limit. If the resistance is higher, fADC must be decreased to increase the sampling

time. So fADC less than 2MHz can be used. It can be noted that for fADC = 1MHz, RADC can be

up to 20 kOhm.

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