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ST9 EXTERNAL MEMORY INTERFACE CONFIGURATION

EXTERNAL BUS TIMING TABLE (MC = 1, BSZ = 1)(Measured on F250)

Note: The timing diagram remains the same for BSZ = 1. We don’t have these measurements

for MC= 0 because we want to promote MC = 1 mode in order to conform with industry

standard.

3.1 MAKING YOUR OWN MEASUREMENTS

Most of these parameters are easy to measure just by writing small programs for writing or

reading to/from the memory. Except for the Data valid to /OEN falling parameter which re-

quires capturing the instant data seen by the microcontroller during a read cycle. To measure

this, a pulse generator is required which can output a pulse with a configurable delay from a

given signal (ALE in this case.) This pulse is used to trigger one of the P0 port pins and data

on port0 is dumped to port4 continuously. So by monitoring port4 and adjusting the delay to

get a ‘1’ at port4, keeping the pulse as narrow as possible the actual moment at which data be-

comes valid for the microcontroller with respect to ALE going low can be captured.

All the measurements for MC=1 have been made between 80% transition of first edge and

20% transition of the second so as to get the minimum values for the measured parameter

By looking at the parameter values for BSZ = 0. It can be concluded that its necessary to add

1 or 2 wait states while operating at high frequencies such as 12MHz otherwise the value of

some of the parameters becomes negative.

N°

Symbol

Parameter

Value (Note)

Unit

Formula

Min.

1

TsA (ALE)

Address Set-up Time before ALE

↓

Tck*Wa+TckH - 28

180

ns

2

ThALE (A)

Address Hold Time after ALE

↓

TckL - 15

26

ns

3

TwALE

ALE High Pulse Width

Tck*Wa+TckH - 24

184

ns

4

TdAz (OEN)

Address Float (P0) to OEN

↓

00

ns

5

TdOEN(Az)

P0 driven after OEN

↑

TckL - 22

20

ns

6TwOEN

OEN Low Pulse Width

Tck*Wd+TckH - 24

184

ns

7TwWEN

WEN Low Pulse Width

Tck*Wd+TckH - 16

192

ns

8TdOEN (DR)

OEN

↓ to Data Valid Delay

Tck*Wd+TckH - 36

172

ns

9

ThDR (OEN)

Data hold time after OEN

↑

00

ns

10

ThOEN(A)

Address (A21:A8) hold time after OEN

↑

00

ns

11

ThWEN(A)

Address (A21:A8) hold time after WEN

↑

00

ns

12

TvA(OEN)

Address (A21:A0) valid to OEN

↑

Tck (Wd+Wa+1.5) - 48

410

ns

13

TvA(WEN)

Address (A21:A0) valid to WEN

↑

Tck (Wd+Wa+1.5) - 42

416

ns

14

TsD (WEN)

Data Set-up time before WEN

↑

Tck*Wd+TckH - 68

140

ns

15

ThWEN(DW)

Data Hold Time after WEN

↑

TckL - 15

26

ns

16

TdALE (WEN)

ALE

↑ to WEN ↑ Delay

Tck (Wd+Wa+1.5) - 34

424

ns

17

TdALE (OEN)

ALE

↑ to OEN ↑ Delay

Tck (Wd+Wa+1.5) - 42

416

ns