LTC1821 datasheet(10/16 Pages) LINER

10 / 16 page

LTC1821

versatility of the interface also allows the use of the input

and DAC registers in a master slave or edge-triggered

configuration. This mode of operation occurs when WR

and LD are tied together. The asynchronous clear pin

resets the LTC1821 to zero scale and the LTC1821-1 to

midscale. CLR resets both the input and DAC registers.

These devices also have a power-on reset. Table 1 shows

the truth table for the LTC1821.

Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to – VREF

APPLICATIONS INFORMATION

VCC

LTC1821

RFB

ROFS

117

RCOM

REF

0.1

µF

0.1

µF

15V

–15V

IOUT

VOUT

22pF

VOUT =

0V TO

–VREF

1821 F01

AGNDF AGNDS

DGND

25 TO 36,

3 TO 6

CLR

DNC* DNC*

CLR

VREF

16-BIT DAC

DATA

INPUTS

0.1

µF

Unipolar Binary Code Table

DIGITAL INPUT

BINARY NUMBER

IN DAC REGISTER

–VREF (65,535/65,536)

–VREF (32,768/65,536) = –VREF/2

–VREF (1/65,536)

LSB

1111 1111

1111

0000 0000

0000

0000 0000

0001

0000 0000

0000

ANALOG OUTPUT

VOUT

MSB

1111

1000

0000

DNC*

V–

V+

*DO NOT CONNECT

Unipolar Mode

(2-Quadrant Multiplying, VOUT = 0V to – VREF)

The LTC1821 can be used to provide 2-quadrant multiply-

ing operation as shown in Figure 1. With a fixed – 10V

reference, the circuit shown gives a precision unipolar 0V

to 10V output swing.

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