UPD6600AGS datasheet(14/36 Pages) NEC

14 / 36 page

µPD6124A, 6600A

Table 13-1. Control Register (P1) (2/2)

(b)

µPD6600A

Bit

D 9

Name

Test mode

–

Be sure to set 0.

Set

Value

Timer

D 8

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

HALT

D.P.

MOD

K I/O

D.P.

AD8

RL A

0 ←

STOP

NOP

AD =0

OSC

RUN

OSC

STOP

/12

AD =1

OSC

OUT

A 3

S-IN

Be sure to

set 0.

D0 .......................... Specifies data to be input to A0 when the accumulator is shifted to the left.

0: A3, 1:S-IN

D1 .......................... Specifies the status of KI/O, as follows:

0: input mode, 1: output mode

D2 .......................... Specifies the status of the timer, as follows:

0: Count stop, 1: Count execution

D3 .......................... Specifies the carrier frequency output from the REM pin.

0: fOSC/8, 1: fOSC/12

D4 .......................... Specify the MSB of the ROM data pointer.

D5 .......................... Be sure to reset them to 0.

D6 .......................... Determines what happen to the oscillation circuit when the HALT instruction is executed.

0: Oscillation does not stop

1: Oscillation stops (STOP mode)

D7 .......................... Be sure to set this bit to 0.

D8, D9 ................. These bits specify test modes. Be sure to set them to 0.

Remark

D0 = D8 = D9 = 0 on reset, and the other bits are undefined.

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