The PWCLK frequency choice

AN4374

12/25

DocID025366 Rev 2

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The PWCLK frequency choice

The PWCLK frequency must be selected to avoid visible flicker on the dimmed LEDs. The

LED PWM frequency is linked to PWCLK frequency and in particular, the PWM frequency is

the PWCLK frequency dived by 65536 (16-bit counter) or 4096 (12-bit counter) related to

the configuration register set-up. To avoid LED flicker, usually, the PWM frequency must be

higher than 100 Hz; to get this set-up, the PWCLK frequency has to be higher than

100x4096 = 410 kHz with CFG-15=1 (12-bit counter), we can round at 500 kHz.

In case of 16-bit counter, the minimum PWCLK frequency must be higher than 100x65536 =

6.5 MHz with CFG-15=0 (16-bit counter), we can round at 7 MHz. Figure 13 shows the

internal PWM signal generation.

Figure 13. PWCLK counter and comparator

AM16862v1