Experimental results

AN2872

18/23

Doc ID 15305 Rev 1

Figure 12.

Indication of current (CH4) and drain voltage (CH1) during short-circuit

4.6

EMC

The following EMC tests of the board were performed:

●

EMI conducting disturbances test for 150 kHZ - 30 MHz (according to EN55022)

●

Surge immunity test (IEC 61000-4-5)

●

Burst immunity test (IEC 61000-4-4).

4.6.1

Surge - IEC 61000-4-5

References: 8) as high power spikes caused by large inductive devices in mains. The input

of the SMPS is charged by a short (20 - 50 µs) but high voltage (0.5 - 4 kV) pulse. The pulse

is applied between L-N and between L (N) - PE.

The surge pulse (typically) causes high inrush current, quickly charging the bulk capacitor in

a standard SMPS. The major risk is overvoltage for input components (capacitors, diodes)

and the main switch in the application. The inrush current can damage the components in

series in the input section of the SMPS (rectifier, fuse, inrush current limiter).

The effect of the surge pulse can be reduced in two ways. The first is to increase the

resistance of the input part (typically possible for low power applications) to reduce inrush

current. Higher input resistance reduces inrush current and consequently the amount of

energy charging the bulk capacitor; therefore the voltage rise over the bulk capacitor is

reduced. The second way is to apply components that reduce the voltage level. Typically it is

possible to use varistors or Transil™ connected to the input (to absorb part of the energy of