AN2381 datasheet(13/47 Pages) STMICROELECTRONICS

13 / 47 page

AN2381

Digital interfaces

13/47

4.1.1

I2C Operation

The transaction on the bus is started through a START signal. A START condition is defined

as a HIGH to LOW transition on the data line while the SCL line is held HIGH (refer to ST

condition in the following paragraph). After this has been transmitted by the Master, the bus

is considered busy. The next byte of data transmitted after the start condition contains the

address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving

data from the slave or transmitting data to the slave (SA subsequence). When an address is

sent, each device in the system compares the first seven bits after a start condition with its

own address. If they match, the device considers itself addressed by the Master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse (SAK

subsequence). A receiver which has been addressed is obliged to generate an

acknowledge after each byte of data has been received.

The I2C embedded inside the LIS3LV02DL behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a salve address is sent (SA),

once a slave acknowledge has been returned (SAK), a 8-bit sub-address will be transmitted

(SUB): the 7 LSB represent the actual register address while the MSB enables address

autoincrement.

If the MSB of the SUB field is ‘1’, the SUB (register address) will be automatically increased

by one to allow multiple data read/write at increasing addresses.

Otherwise if the MSB of the SUB field is ‘0’, the SUB will remain unchanged and multiple

read/write on the same address can be performed.

If the LSB of the slave address was ‘1’ (read), a repeated START (SR) condition will have to

be issued after the sub-address byte; if the LSB is ‘0’ (write) the Master will transmit to the

slave with direction unchanged.

4.1.2

I2C Subsequences

In order to better define subsequences and to clarify line SCL and SDA behavior, a

description containing discrete value of SCL and SDA will follow. In column there is the

value present on line SCL and SDA in discrete timing. These simple subsequences are

used to realize complex commands described in the following paragraph.

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