Layout Considerations.

Special attention must be taken to avoid overvoltages at Vs and additional negative voltages to the

SENSE pins and noise due to distributed inductance. Thus the input capacitor must be connected close

to the Vs pins with symmetrical paths. The paths between the SENSE pins and the input capacitor

ground have to be minimized and symmetrical . The sensing resistors must be non-inductive. The de-

vice GND has to be connected with a separate path to the input capacitor ground.

Figure 20. Component side.

Figure 19. Application Board Layout.

AN1088 APPLICATION NOTE

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