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AN557 APPLICATION NOTE

It must be remembered, however, that because of the high output impedance of the error amplifier, a sec-

ond pole is also present:

18)

We normally suggest a high value for R1 to reduce the value of the capacitor C1 and allocate the pole P2

at the highest possible frequency. The essential limitation to the max value of R1 is the offset introduced

by the input bias current of the error amplifier. In the case of output voltage regulated higher than 5.1V, an

external divider should be introduced. It’s than possible to introduce a second zero using the following net-

work:

Figure 18. Compensation network for output voltages higher than 5.1V

Two zeros and two poles are introduced:

19)

Where

APPLICATION EXAMPLE

Consider the block diagram of fig. 19, representing the internal control loop section, with the application

values:

Fswitch = 200KHz, L = 100

µH, C = 1000µF, Po = 50W, Vo = 5.1V, Io = 10A and Fo = 500Hz. Gloop = PWM

× Filter

Figure 19. Block diagram used in stability calculation

Π C1

------------------

Π R

o Cc

---------------------------

Π R1 C1

-----------------------------

Π R

o Cc

---------------------------

Π Rx C1

-----------------------------

R1 R 2

⋅

----------------------

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