PD78F9210CS_15 datasheet(17/30 Pages) RENESAS

17 / 30 page

Preliminary Product Information U18551EJ2V0PM

µ PD78F9210CS, 78F9211CS, 78F9212CS

DC Characteristics (TA =

−40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

When A/D converter is stopped

6.1

12.2

fX = 10 MHz

VDD = 5.0 V

±10%Note 4

When A/D converter is operating

7.6

15.2

When A/D converter is stopped

5.5

11.0

fX = 6 MHz

VDD = 5.0 V

±10%Note 4

When A/D converter is operating

14.0

When A/D converter is stopped

3.0

6.0

IDD1

Note 3

Crystal/ceramic

oscillation,

external clock

input oscillation

operating

mode

Note 6

fX = 5 MHz

VDD = 3.0 V

±10%Note 5

When A/D converter is operating

4.5

9.0

When peripheral functions are stopped

1.7

3.8

fX = 10 MHz

VDD = 5.0 V

±10%Note 4

When peripheral functions are operating

6.7

When peripheral functions are stopped

1.3

3.0

fX = 6 MHz

VDD = 5.0 V

±10%Note 4

When peripheral functions are operating

6.0

When peripheral functions are stopped

0.48

IDD2

Crystal/ceramic

oscillation,

external clock

input HALT

mode

Note 6

fX = 5 MHz

VDD = 3.0 V

±10%Note 5

When peripheral functions are operating

2.1

When A/D converter is stopped

5.0

10.0

IDD3

Note 3

High-speed

internal oscillation

operating

mode

Note 7

fX = 8 MHz

VDD = 5.0 V

±10%Note 4

When A/D converter is operating

6.5

13.0

When peripheral functions are stopped

1.4

3.2

IDD4

High-speed

internal oscillation

HALT mode

Note 7

fX = 8 MHz

VDD = 5.0 V

±10%Note 4

When peripheral functions are operating

5.9

When low-speed internal oscillation

is stopped

3.5

20.0

VDD = 5.0 V

±10%

When low-speed internal oscillation

is operating

17.5

32.0

µA

When low-speed internal oscillation

is stopped

3.5

15.5

Supply

current

Note 2

IDD5

STOP mode

VDD = 3.0 V

±10%

When low-speed internal oscillation

is operating

11.0

26.0

µA

Notes 1.

Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on

clear (POC) circuit is 2.1 V

±0.1 V.

Total current flowing through the internal power supply (VDD). However, the current that flows through the

pull-up resistors of ports is not included.

IDD1 and IDD3 includ peripheral operation current.

When the processor clock control register (PCC) is set to 00H.

When the processor clock control register (PCC) is set to 02H.

When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using

the option byte.

When high-speed internal oscillation clock is selected as the system clock source using the option byte.

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