1. ABSTRACT

This application note provides interfacing solutions between some of the popular standard differential

logic families and LVDS technology.

2. INTRODUCTION.

LVDS signals are differential signal technologies with a swing of 250 to 400mV and a DC offset of 1.2V.

They are used today to interface between CMOS and BICMOS ASICs supplied with 3.3V or cell. LVDS,

LVPECL, PECL and ECL are all differential technologies but with different swings and offsets (see figure

1).

Figure 1: Voltage Levels

This application note will show the possible interface between the LVDS device and the other differential

signal levels listed above. It will also give suggestions on how to interface supplied positive and negative

devices.

Due to its speed capability, the application board requires a proper technical high speed layout,

otherwise the system performance will be reduced.

As a general guideline to get better performance from the PCB, the transmission striplines should be

adapted as specified:

- The input line must be routed away from the output lines or separated from the larger swings;

- the lines must be as short as possible;

- the termination line resistors must be the nearest to the receiver;

- the use of surface mount components are recommended.

PECL

LVPECL

ECL

LVDS

February 2001

1/9

AN1318

APPLICATION NOTE

INTERFACING BETWEEN LVDS AND HIGH

SPEED DIFFERENTIAL LOGIC FAMILIES

G. Noviello