AN4199 datasheet(16/23 Pages) STMICROELECTRONICS

tên linh kiện	AN4199

Giải thích chi tiết về linh kiện	Two-layer demonstration board based on the STA333IS

PDF	23 Pages

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16 / 23 page

Design guidelines for schematic and PCB layout

AN4199

16/23

DocID023917 Rev 1

Design guidelines for schematic and PCB layout

6.1

General



Absolute maximum rating: 20 V



Bypass capacitor 100 nF in parallel to 1 µF and 10 µF for each power VCC branch.

Preferable dielectric is X7R.



Vdd and ground for the digital section should be separated from the other power

supply.



Coil saturation current compatible with the peak current of the application

6.2

Decoupling capacitors

The decoupling capacitors can be shared for each VCC branch. The decoupling capacitors

must be placed as close as possible to the IC pins.

6.3

Output filter

Figure 17. Output filter

6.3.1

Snubber network

The snubber circuit must be optimized for the specific application. Starting values are

330 pF in series to 22

.

The power dissipation in this network can be defined by the following formula which

considers the power supply, frequency and capacitor value:

P = C · FreqPWM · (2 · Vout)

This power is dissipated on the series resistance.

SNUBBER

MAIN FILTER

DAMPING NETWORK

AN4199 bảng dữ liệu(PDF) 16 Page - STMicroelectronics