R5F36506NFA datasheet(82/115 Pages) RENESAS

82 / 115 page

R01DS0031EJ0210 Rev.2.10

Page 82 of 111

Jul 31, 2012

M16C/65 Group

5. Electrical Characteristics

Figure 5.17

Timing Diagram

Memory Expansion Mode and Microprocessor Mode

(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )

BCLK

CSi

ADi

ALE

BHE

ADi

/DBi

Read timing

BCLK

CSi

ADi

ALE

BHE

ADi

/DBi

Data output

Write timing

Address

Data input

Address

= V

= 5V

CC1

CC2

td(BCLK-CS)

25ns(max.)

tcyc

(0.5 × t

-10)ns(min.)

cyc

th(RD-CS)

th(BCLK-CS)

0ns(min.)

(0.5 × t

-25ns(min.)

cyc

td(AD-ALE)

(0.5 × t

-15ns(min.)

cyc

th(ALE-AD)

tdz(RD-AD)

8ns(max.)

{(n-0.5) × t

-45}ns(max.)

cyc

tac3(RD-DB)

tsu(DB-RD)

th(RD-DB)

0ns(min.)

td(AD-RD)

th(BCLK-AD)

0ns(min.)

15ns(max.)

td(BCLK-ALE)

th(BCLK-ALE)

-4ns(min.)

td(BCLK-AD)

25ns(max.)

th(RD-AD)

(0.5 × t

-10)ns(min.)

cyc

25ns(max.)

td(BCLK-RD)

0ns(min.)

th(BCLK-RD)

tcyc

td(BCLK-CS)

25ns(max.)

(0.5 × t

-10)ns(min.)

cyc

th(WR-CS)

th(BCLK-CS)

0ns(min.)

td(BCLK-DB)

40ns(max.)

th(BCLK-DB)

0ns(min.)

(0.5 × t

-25ns(min.)

cyc

td(AD-ALE)

{(n-0.5) × t

-40}ns(min.)

cyc

td(DB-WR)

(0.5 × t

-10)ns(min.)

cyc

th(WR-DB)

td(BCLK-AD)

25ns(max.)

th(BCLK-AD)

0ns(min.)

15ns(max.)

td(BCLK-ALE)

th(BCLK-ALE)

-4ns(min.)

0ns(min.)

td(AD-WR)

th(WR-AD)

(0.5 × t

-10)ns(min.)

cyc

25ns(max.)

td(BCLK-WR)

0ns(min.)

th(BCLK-WR)

n: 2 (when 2 waits)

3 (when 3 waits)

Measuring conditions

= V

= 5V

CC1

CC2

Input timing voltage: V = 0.8 V, V

= 2.0 V

Output timing voltage: V

= 0.4 V, V

= 2.4 V

40ns(min.)

WR, WRL,

WRH

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