12

performance of Figure 13 and Figure 14 is basically the

same, however leaving the center tap of Figure 14 floating

allows the circuit to find a more balanced virtual ground,

theoretically improving the even order harmonic rejection,

but likely reducing the signal swing available due to the

output voltage compliance range limitations.

Propagation Delay

The converter requires two clock rising edges for data to be

represented at the output. Each rising edge of the clock

captures the present data word and outputs the previous

data. The propagation delay is therefore 1/CLK, plus <2ns of

processing. See Figure 15.

Test Service

Intersil offers customer-specific testing of CommLink

converters with a service called Testdrive. To submit a

request, fill out the Testdrive form at

www.intersil.com/testdrive. Or, send a request to the

technical support center.

ISL5829

FIGURE 13. OUTPUT LOADING FOR DATASHEET

MEASUREMENTS

OUTA

OUTB

LOAD SEEN BY THE TRANSFORMER

1:1

AT EACH OUTPUT

FIGURE 14. ALTERNATIVE OUTPUT LOADING

ISL5829

OUTA

OUTB

AT EACH OUTPUT

LOAD SEEN BY THE TRANSFORMER

Timing Diagram

FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

CLK

50%

D11-D0

ISL5829