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Waveforms

FIGURE 17. TIMING RELATIVE TO WR OR WITH CE

FIGURE 18. OUTPUT RISE AND FALL TIMES

NOTE: CASZ, OFM, OE are signals that must remain constant with

respect to REFCLK until the part is reset. In the write mode,

either CE or WR must be clocked while the other is tied low.

In read mode, either CE or RD must be clocked while the oth-

er is tied low. Never tie all three interface signals (CE, RD and

WR) low at the same time.

FIGURE 19. TIMING RELATIVE TO REFCLK

FIGURE 20. OUTPUT ENABLE/DISABLE

FIGURE 21. TIMING RELATIVE TO READ OR TO CE

WR OR-ED CE

A9-0

FIFORDY

C15-0

0.8V

2.0V

REFCLK

CAS(15:0),

SYNCIN

SAMPCLK, SYNCOUT,

FIFORDY

OUT(15:0)

C15-0

RD OR’ed CE

A9-0

1.7V

1.3V

1.5V

1.5V

OUT(15:0)

OE

HSP50215