HSP50214BVC datasheet(13/60 Pages) INTERSIL

13 / 60 page

3-13

The integration period counter can be set up to run

continuously or to count down and stop. Continuous integration

counter operation lets the counter run, with sampling occurring

every time the counter reaches zero. Because the processor

samples the detector read port asynchronous to the CLKIN,

data can be missed unless the status bit is monitored by the

processor to ensure that a sample is taken for every integration

count down sequence.

Additionally, in the HSP50214B, the ability to align the

start/restart of the input level detector integration period with

an external event is provided. This allows the sync signals,

which are synchronized to external events, to be used to align

all of the gain adjustments or measurements. If Control Word

27, Bit 17 is set to a logic one, the SYNCIN1 signal will cause

the input level detector to start/restart its integration period. If

Control Word 27, Bit 17 is set to a logic zero, control of the

start/restart of the input level detector integration period does

not respond to SYNCIN1.

In the count down and stop mode, the microprocessor read

commands can be synchronized to system events, such as the

start of a burst for a TDMA application. The integration counter

can be started at any time by writing to Control Word 2. At the

end of the integration period (counter = 0000), the upper 23 bits

of the accumulator are transferred to a holding register for

reading by the microprocessor. Note that it is not the restarting

of the counter (by writing to Control Word 2) that latches the

current value, but the end of the integration count. When the

accumulator results are latched, a bit is set in the Status

byte of the 23 bits clears the status bit. See the Microprocessor

Read Section. Figure 11 illustrates a typical AGC detection

process.

FIGURE 9.

INPUT

GATING

LOGIC

|X|

ACCUMULATOR

CLKIN

INPUT_THRESHOLD

†

INTEGRATION_INTERVAL

†

START

†

INTEGRATION_MODE

†

IN(13:0)

“0”

µPROC

ADDR(2:0)

CONTINUOUS

SINGLE

COUNTER

† Controlled via microprocessor interface.

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

-20

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

-6dB

-12dB

-18dB

-24dB

-30dB

-36dB

-42dB

-48dB

-54dB

-60dB

-66dB

-72dB

-78dB

214

213

212

211

210

217

216

215

218

2-1

2-2

2-3

2-4

214

213

212

211

210

217

216

215

218

FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING

HSP50214B

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