HIP4020IB datasheet(3/8 Pages) INTERSIL

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HIP4020

Response Time: VEN to VOUT

IO = 0.5A (Note 2)

Turn-On: Prop Delay

tPLH

2.5

µs

Rise Time

-4-

µs

Turn-Off: Prop Delay

tPHL

0.1

µs

Fall Time

0.1

µs

NOTES:

1. VSS is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in

reference to the VSS common ground by using a split supply for VDD (positive) to VSSA and VSSB (negative). For an uneven split in the

supply voltage, the Maximum Negative Output Supply Voltage for VSSA and VSSB is limited by the Maximum VDD to VSSA or VSSB ratings.

Since the VDD pins are internally tied together, the voltage on each VDD pins must be equal and common.

2. Refer to the Truth Table and the VEN to VOUT Switching Waveforms. Current, IO refers to IOUTA or IOUTB as the Output Load current. Note

that ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1, A2, ENA or B1,

B2, ENB inputs. Refer to the Terminal Information Table for external pin connections to establish mode control switching. Figure 1 shows

a typical application circuit used to control a DC Motor.

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

12, 19

VDD

Positive Power Supply pins; internally common and externally connect to the same Positive Supply

(V+).

VSSA

Negative Power Supply pin; Negative or Ground return for Switch Driver A; externally connect to the

Supply (V-).

VSSB

Negative Power Supply pin; Negative or Ground return for Switch Driver B; externally connect to the

Supply (V-).

6VSS

Common Ground pin for the Input Logic Control circuits. May be used as a common ground with

VSSA and VSSB.

8, 5

A1, B1

Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively.

When connected, A1 and B1 can be controlled from the same logic signal to change the directional

rotation of a motor.

9, 3

A2, B2

Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2

can be controlled from the same logic signal to activate Dynamic Braking of a motor.

7, 4

ENA, ENB

Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respec-

tive output is in a high impedance (Z) off-state. Since each Switch Driver is independently controlled,

OUTA and OUTB may be a separately PWM controlled as Half H-Switch Drivers.

14, 17

OUTA, OUTB

Respectively, Switch Driver A and Switch Driver B Output pins.

ILF

Current Limiting Fault Output Flag pin; when in a high logic state, signifies that Switch Driver A or B

or both are in a Current Limiting Fault Mode.

Electrical Speciﬁcations

TA = 25

oC, V

DD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Speciﬁed (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

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