2

HIP0063

FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING HOW THE GATE DRIVE OUTPUT AND DRAIN MONITOR

INPUT CONTROLS TWO HIP0061 THREE FET ARRAYS

FIGURE 2. SPI DATA AND CLOCK TIMING DIAGRAM. SERIAL COMMUNICATION IS INITIATED WHEN CS GOES LOW AND SCK

IS LOW. 8 OR 16 BITS OF DATA IS CLOCKED INTO SI ON THE LEADING EDGE OF SCK. DATA IS CLOCKED OUT OF

SO ON THE TRAIL EDGE OF SCK. WHEN CS GOES HIGH, DATA IS LATCHED TO CONTROL EACH CHANNEL

DRAIN MONITOR

GATE DRIVER

DATA

DRIVE CONTROL

5V

GND

PI0

PI1

PI2

PI3

PI4

PI5

14V

2 - HIP0061

HARDWARE GENERATED OR CUSTOM LOGIC

SOURCED PWM CONTROL SIGNAL INPUTS

POR, TIMING OSC,

BAND GAP REF.,

OVER-VOLT. DET.

D5

G5

S0

SI

SCK

CS

HLOS (SEL)

HPW01

HPW45

HIP0063

D4

G4

D3

G3

D2

G2

D1

G1

D0

G0

LATCH

OR EQUIVALENT

CHANNEL #0

14V

DRAIN MONITOR

GATE DRIVER

DATA

DRIVE CONTROL

LATCH

CHANNEL #1

DRAIN MONITOR

GATE DRIVER

DATA

DRIVE CONTROL

LATCH

CHANNEL #2

DRAIN MONITOR

GATE DRIVER

DATA

DRIVE CONTROL

LATCH

CHANNEL #3

DRAIN MONITOR

GATE DRIVER

DATA

DRIVE CONTROL

LATCH

CHANNEL #4

DRAIN MONITOR

GATE DRIVER

DATA

DRIVE CONTROL

LATCH

CHANNEL #5

PARALLEL/

SERIAL IN,

SHIFT REG.

CONTROL

PARALLEL/

SERIAL IN,

SHIFT REG.

CONTROL

PARALLEL/

SERIAL IN,

SHIFT REG.

CONTROL

PARALLEL/

SERIAL IN,

SHIFT REG.

CONTROL

PARALLEL/

SERIAL IN,

SHIFT REG.

CONTROL

PARALLEL/

SERIAL IN,

SHIFT REG.

CONTROL

HLOS

SPI

CS

SCK

(CPOL = 0, CPHA = 1)

INTERNAL STROBE FOR DATA CAPTURE

MSB

6

5

4

3

2

1

LSB