REV. A

ADE7759

–33–

000

00

00

0

765

4

3210

ADDR: 10H

AEHF

(ACTIVE ENERGY REGISTER HALF FULL)

SAG

(LINE VOLTAGE SAG DETECT)

CYCEND

(END OF LINE CYCLE ENERGY ACCUMULATION)

WSMP

(WAVEFORM SAMPLING)

AEOF

(ACTIVE ENERGY REGISTER OVERFLOW)

NOT USED

TEMP

(TEMPERATURE REGISTER READY)

ZX

(ZERO CROSSING DETECTED)

NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS

Figure 50. Interrupt Enable Register

CH1OS Register (08H)

The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in Chan-

nel 1, and Bits 0 to 5 indicate the amount of the offset correction in Channel 1. Table VIII summarizes the function of this register.

Table VIII. CH1OS Register

Bit Location

Bit Mnemonic

Description

0 to 5

OFFSET

The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1

ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude

of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset

correction is positive and a 1 indicates the offset correction is negative.

6

Not Used

This bit is unused.

7

INTEGRATOR

This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched

on by setting this bit. This bit is set to be 1 on default.

100

00

00

0

765

4

3210

ADDR: 08H

CH1OS REGISTER*

SIGN AND MAGNITUDE CODED

OFFSET CORRECTION BITS

DIGITAL INTEGRATOR SELECTION

1 = ENABLE

0 = DISABLE

NOT USED

*REGISTER CONTENTS SHOW POWER-ON DEFAULT

Figure 51. CH1OS Register

010

00

00

0

765

4

3210

ADDR: 04H/RESET: 05H

AEHF

(ACTIVE ENERGY REGISTER HALF FULL)

SAG

(LINE VOLTAGE SAG DETECT)

CYCEND

(LINE CYCLE ENERGY ACCUMULATION END)

WSMP

(WAVEFORM SAMPLING)

AEOF

(ACTIVE ENERGY REGISTER OVERFLOW)

TEMP

(TEMPERATURE REGISTER READY)

ZX

(ZERO CROSSING DETECTED)

RESET

(END OF A HARDWARE OR SOFTWARE RESET)

NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS

Figure 49. Interrupt Status Register