ADAV802_15 datasheet(28/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 28 of 53

Table 26. SRC & Clock Control Register

CLK2-

CLK1-

MCLK-

SRCDIV1

SRCDIV

DIV1

DIV0

DIV1

DIV0

SEL1

SEL0

ADDRESS = 0000000

SRCDIV1-0

Divides the SRC Master Clock

00 = The SRC Master Clock is not divided

01 = The SRC Master Clock is divided by 1.5

10 = The SRC Master Clock is divided by 2

11= The SRC Master Clock is divided by 3

CLK2DIV1-0

Clock Divider for Internal Clock 2 (ICLK2)

00 = Divide by 1

01 = Divide by 1.5

10 = Divide by 2

11 = Divide by 3

CLK1DIV1-0

Clock Divider for Internal Clock 1 (ICLK1)

00 = Divide by 1

01 = Divide by 1.5

10 = Divide by 2

11 = Divide by 3

MCLKSEL1-0

Clock Selection for the SRC Master Clock

00 = Internal Clock 1

01 = Internal Clock 2

10 = PLL Recovered Clock (512 × fS)

11 = PLL Recovered Clock (256 × fS)

Table 27. SPDIF Loopback Control Register

RES

TxMUX

ADDRESS = 0000011

TxMUX

Selects the source for SPDIF Output (DITOUT)

0 = SPDIF Transmitter - Normal Mode

1 = DIRIN - Loopback Mode

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