AD14060L datasheet(21/48 Pages) AD

21 / 48 page

AD14060/AD14060L

Rev. B | Page 21 of 48

Table 17. 2× CLK Speed Operation

5 V

3.3 V

Parameter

Min

Max

Min

Max

Unit

Receive

Timing Requirements:

tSLDCL

Data Setup before LCLK Low

2.75

2.25

tHLDCL

Data Hold after LCLK Low

2.25

tLCLKIW

LCLK Period (2× Operation)

tCK/2

tLCLKRWL

LCLK Width Low

4.6

5.25

tLCLKRWH

LCLK Width High

4.25

4.5

Switching Characteristics:

tDLAHC

LACK High Delay after CLKIN High

18 + DT/2

31.5 + DT/2

18 + DT/2

30.5 + DT/2

tDLALC

LACK Low Delay after LCLK High1

17.8

Transmit

Timing Requirements:

tSLACH

LACK Setup before LCLK High

20.25

tHLACH

LACK Hold after LCLK High

−6.5

Switching Characteristics:

tDLCLK

LCLK Delay after CLKIN

tDLDCH

Data Delay after LCLK High

3.25

2.75

tHLDCH

Data Hold after LCLK High

−2

tLCLKTWL

LCLK Width Low

(tCK/4) − 1

(tCK/4) + 1.5

(tCK/4) − 0.75

(tCK/4) + 1.5

tLCLKTWH

LCLK Width High

(tCK/4) − 1.5

(tCK/4) + 1

(tCK/4) − 1.5

(tCK/4) + 1

tDLACLK

LCLK Low Delay after LACK High

(tCK/4) + 9

(3 × tCL/4) + 17

(tCK/4) + 9

(3 × tCL/4) + 17

1 LACK goes low with tDLALC relative to the rising edge of LCLK after the first nibble is received. LACK does not go low, if the receiver’s link buffer is not about to fill.

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