CDP1854ACSLASH3 datasheet(20/21 Pages) INTERSIL

20 / 21 page

5-61

NOTES:

1. The holding register is loaded on the trailing edge of THRL.

2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTHC

after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + tCD later.

FIGURE 10. MODE 0 TRANSMITTER TIMING DIAGRAM

T CLOCK

THRL

SDO

THRE

TSRE

T BUS 0

T BUS 7

tCC

tCL

tCH

tTHC

tTHTH

tCD

tCT

tTTS

tTTHR

tTD

tDT

DATA

tCD

1ST DATA BIT

TRANSMITTER SHIFT

(NOTE 2)

TRANSMITTER HOLDING

(NOTE 1)

NOTES:

1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next

high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.

2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding

FIGURE 11. MODE 0 RECEIVER TIMING DIAGRAM

R CLOCK

R BUS 7

DAR

tCC

tCL

tCH

tDC

START BIT

tDDA

tCDV

CLOCK 7 1/2

SAMPLE

(NOTE 1)

SDI

STOP BIT 1

CLOCK 7 1/2 LOAD

HOLDING REGISTER

tCDA

tDD

tCOE

tCPE

tCFE

R BUS 0 -

(NOTE 2)

PARITY

FIGURE 12. SERIAL DATA WORD FORMAT

NEXT DATA WORD

STOP BITS 1, 1-1/2 OR 2

PARITY BIT

DATA

MSB

5 - 8 DATA BITS

DATA

LSB

START BIT

16 / fCLOCK

CDP1854A, CDP1854AC

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