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CDP1883CE bảng dữ liệu(PDF) 5 Page - Intersil Corporation

tên linh kiện CDP1883CE
Giải thích chi tiết về linh kiện  CMOS 7-Bit Latch and Decoder Memory Interfaces
PDF  6 Pages
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nhà sản xuất  INTERSIL [Intersil Corporation]
Trang chủ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1883CE bảng dữ liệu(HTML) 5 Page - Intersil Corporation

  CDP1883CE Datasheet HTML 1Page - Intersil Corporation CDP1883CE Datasheet HTML 2Page - Intersil Corporation CDP1883CE Datasheet HTML 3Page - Intersil Corporation CDP1883CE Datasheet HTML 4Page - Intersil Corporation CDP1883CE Datasheet HTML 5Page - Intersil Corporation CDP1883CE Datasheet HTML 6Page - Intersil Corporation  
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
CLOCK to Address
tCLA
5
-
100
175
-
100
175
ns
10
-
65
125
-
-
-
ns
Memory Address to Chip Select
tMACS
5
-
100
175
-
100
175
ns
10
-
75
125
-
-
-
ns
Memory Address to Address
tMAA
5
-
80
125
-
80
125
ns
10
-
40
60
-
-
-
ns
NOTES:
1. Typical values are for TA = 25
oC.
2. Maximum limits of minimum characteristics are the values above which all devices function.
FIGURE 1. CDP1883 TIMING WAVEFORMS
Dynamic Electrical Specifications TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF.
See Figure 1 (Continued)
PARAMETER
VDD
(V)
CDP1883
CDP1883C
UNITS
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
VALID CHIP ENABLE
(A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
(B) MEMORY ADDRESS SETUP AND HOLD TIME
tCECS
tCECS
tCLMA
tMACL
tCLCL
tCLCS
tCLA
A8 - A12
CS0, CS1, CS2, CS3
CLOCK
MA0 - MA5
CS0, CS1, CS2, CS3
CE
tMACS
tMACS
tMAA
tMAA
CDP1883, CDP1883C



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