4-8

then executes an input or a load instruction, depending on the

mapping technique used. In either case the proper code must

be asserted on the RAO, RA1, and CS lines to read the buffer

register (see Table 6).

The INT line is deactivated on the leading edge of TPB. The

trailing edge of TPB sets the RDY line to signal the periph-

eral that the port is ready to be loaded with new data. If RDY

is low when the input mode is entered (i.e. after a reset), a

“dummy” read must be done to set RDY high and signal the

peripheral device that the port is ready to be loaded.

Output Mode

A peripheral STROBE pulse sent to the PlO generates an

interrupt to signal the CPU that the peripheral device is

ready for data. The CPU executes the proper output or store

instruction. Data are then read from memory and placed on

the bus. The data are latched into the port buffer at the end

of the window when RE/WE = 0 and WR/RE = 1. The RDY

line is also set at this time, indicating to the peripheral that

there is data in the port buffer. The INT line is deactivated at

the beginning of the window. After the peripheral reads valid

port data, it can send another STROBE pulse, clearing the

RDY line and activating the INT line as in the input mode.

Bidirectional Mode

This mode programs port A to function as both an input and

output port. The bidirectional feature allows the peripheral to

control port direction by using both sets of handshake signals.

The port A handshaking pins are used to control input data

from peripheral to PlO, while the port B handshaking pins are

used to control output data from PlO to peripheral. Data are

transferred in the same manner as the input and output

modes. Since A INT is used for both input and output, the sta-

tus register must be read to determine what condition caused

A INT to be activated (see Table 5).

Bit-Programmable Mode

This mode allows individual bits of port A or port B to be

programmed as inputs or outputs. To output data to bits

programmed as outputs, the CPU loads a data byte into the

8-bit port as in the output mode (no handshaking). Only bits

programmed for outputs latch this data. Data must be stable

when reading from bits programmed as inputs, since the

input bits do not latch. When the CDP1851 inputs data to the

CPU the CPU also reads the output bits latched during the

last output cycle. The RDY and STROBE lines may be used

for I/O by using the STROBE/RDY I/O control byte in Table 2.

An additional feature available in the bit-programmable

mode is the ability to generate interrupts based on

input/output byte combinations. These interrupts can be

programmed to occur on logic conditions (AND, OR, NAND,

and NOR) generated by the eight I/O lines of each port (The

STROBE and RDY lines cannot generate interrupts).

A0

A1

A2

A3

A4

A5

A6

A7

INT

BUS 0-7

CDP1800

FAMILY

µP

TPA

MWR

MRD

TPB

10k

Ω

RA0

RA1

A RDY

PORT A0 - A7

PORT B0 - B7

A INT

BUS 0-7

PIO

NO. 1

CLOCK

RD/WE

WR/RE

TPB

CDP1851

B INT

CS

B RDY

A STROBE

B STROBE

RA0

RA1

A RDY

PORT A0 - A7

PORT B0 - B7

PIO

NO. 2

CLOCK

RD/WE

WR/RE

TPB

CDP1851

B RDY

A STROBE

B STROBE

CS

A INT

B INT

ADDRESS REGISTER

ADDRESS

SELECTS

8001

No. 1 Control/Status Reg

8002

No. 1 Port A

8003

No. 1 Port B

8004

No. 2 Control/Status Reg

8008

No. 2 Port A

800C

No. 2 Port B

FIGURE 2. MEMORY SPACE I/O. THIS CONFIGURATION ALLOWS UP TO FOUR CDP1851s TO OCCUPY MEMORY SPACE 8XXX WITH

NO ADDITIONAL HARDWARE (A4-A5 AND A6-A7 ARE USED AS RA0 AND RA1 ON THE THIRD AND FOURTH PIO’s)

CDP1851, CDP1851C